Draper Senior ASIC DFT Engineer in Cambridge, Massachusetts
Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 1,800 employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.
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Draper Laboratory is seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Senior Digital ASIC DFT Engineer, you will be responsible for designing high-performance digital ASICs in advanced technologies—14nm FinFET, 22FDX, etc. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas. The applicant should have significant experience with ASIC DFT (Design-for-Test) and DFD (Design-for-Debug) spanning the design, implementation and testing of complex ASICs and SoCs. Familiarity with MBIST, LBIST, JTAG, and scan testing both pre- and post-silicon in SoC designs is required. The ideal candidate will have proven experience implementing and deploying these techniques to reduce cost, increase yield and reduce debug time in advanced nodes.
Applicants should possess solid skills in back-end digital systems design with experience in design flows from Cadence or Synopsys. Demonstrated experience with successful tapeouts at advanced nodes is required. Experience leading and managing design teams and training junior staff is also required.
Leading and training junior staff and small teams
DFT insertion including scan, LBIST, MBIST and JTAG
Perform ATPG simulations and testing
Lead post-silicon test and debug efforts
Develop methodologies, processes and tools for DFT for deployment on several projects
Train junior staff in DFT methodologies
BSEE or equivalent education
15+ years of relevant experience
VHDL or Verilog experience
Fluent in scripting languages
Demonstrated experience with DFT
Experience developing DFT flows
MSEE with 20+ years experience
Experience leading teams
Experience with other aspects of ASIC design
- Applicants selected for this position will be required to obtain and maintain a government security Government security clearance requires proof of US citizenship.
External Company Name: The Charles Stark Draper Laboratory Inc